[riot-commits] [RIOT-OS/RIOT] c404bd: k60: Add workaround for errata e4218

Joakim Nohlgård joakim.nohlgard at eistec.se
Fri Oct 30 07:33:32 CET 2015


  Branch: refs/heads/master
  Home:   https://github.com/RIOT-OS/RIOT
  Commit: c404bd97ad42e5baecb65669875f22499e6284f5
      https://github.com/RIOT-OS/RIOT/commit/c404bd97ad42e5baecb65669875f22499e6284f5
  Author: Joakim Gebart <joakim.gebart at eistec.se>
  Date:   2015-10-25 (Sun, 25 Oct 2015)

  Changed paths:
    M cpu/k60/vector.c

  Log Message:
  -----------
  k60: Add workaround for errata e4218

e4218: SIM/FLEXBUS: SIM_SCGC7[FLEXBUS] bit should be cleared when the
FlexBus is not being used.

Errata type: Errata

Description:

The SIM_SCGC7[FLEXBUS] bit is set by default. This means that the
FlexBus will be enabled and come up in global chip select mode. With
some code sequence and register value combinations the core could
attempt to prefetch from the FlexBus even though it might not actually
use the value it prefetched. In the case where the FlexBus is
unconfigured, this can result in a hung bus cycle on the FlexBus.

Workaround:

 - If the FlexBus is not being used, disabled the clock to the FlexBus
   during chip initialization by clearing the SIM_SCGC7[FLEXBUS] bit.
 - If the FlexBus will be used, then enable at least one chip select as
   early in the chip initialization process as possible.


  Commit: 76bddaf21346d21845326202d76a390023219b10
      https://github.com/RIOT-OS/RIOT/commit/76bddaf21346d21845326202d76a390023219b10
  Author: Joakim Nohlgård <joakim.nohlgard at eistec.se>
  Date:   2015-10-30 (Fri, 30 Oct 2015)

  Changed paths:
    M cpu/k60/vector.c

  Log Message:
  -----------
  Merge pull request #3283 from gebart/pr/kinetis-errata-e4218

k60: Add workaround for errata e4218


Compare: https://github.com/RIOT-OS/RIOT/compare/6db89a616f4d...76bddaf21346


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