[riot-commits] [RIOT-OS/RIOT] 35635e: stm32f3: periph: uart: add misssing uart overrun h...

Oleg Hahm oleg at hobbykeller.org
Mon Feb 22 12:26:01 CET 2016


  Branch: refs/heads/master
  Home:   https://github.com/RIOT-OS/RIOT
  Commit: 35635e4039df801b068f640470d5431883bc14a2
      https://github.com/RIOT-OS/RIOT/commit/35635e4039df801b068f640470d5431883bc14a2
  Author: Steffen Pengel <Steffen.Pengel at gmail.com>
  Date:   2016-02-21 (Sun, 21 Feb 2016)

  Changed paths:
    M cpu/stm32f3/periph/uart.c

  Log Message:
  -----------
  stm32f3: periph: uart: add misssing uart overrun handling

On overrung the ORE bit in the ORECF register is set.
An overrun error occurs when a character is received when RXNE has not been reset. Data
can not be transferred from the shift register to the RDR register until the RXNE bit is
cleared. The ORE bit is reset by setting the ORECF bit in the ICR register.

In case the ORE bit isn't cleared, the isr_handler() routine is called
continuously. Which prevents the system from normal scheduling.


  Commit: 0ffed1d100836cc880f6fc1892e03e098f4ad5ae
      https://github.com/RIOT-OS/RIOT/commit/0ffed1d100836cc880f6fc1892e03e098f4ad5ae
  Author: Oleg Hahm <oleg at hobbykeller.org>
  Date:   2016-02-22 (Mon, 22 Feb 2016)

  Changed paths:
    M cpu/stm32f3/periph/uart.c

  Log Message:
  -----------
  Merge pull request #4868 from steffen-p/stm32f3_periph_uart_deadlock_on_overrun

stm32f3: periph: uart: add misssing uart overrun handling


Compare: https://github.com/RIOT-OS/RIOT/compare/bf1d31a62b04...0ffed1d10083


More information about the commits mailing list