[riot-devel] RIOT OS port for the icoBoard FPGA board - icoSoC / picorv32 RISC-V platform

Koen Zandberg koen at bergzand.net
Wed Sep 9 14:09:43 CEST 2020


Hi Tomas,

On 03-09-2020 21:04, Tomas Styblo wrote:
> Hi guys,
> so far it's only an experiment, but I've started porting RIOT OS to
> the icoBoard Lattice FPGA / icoSoC / picorv32 RISC-V softcore CPU
> platform.
>
> The Lattice chip used on the icoBoard is probably the only FPGA device
> supported by open source tools. And it will be the first FPGA device
> supported by RIOT OS (AFAIK)

I think you're right with this. I haven't heard of anybody running RIOT
on an FPGA softcore before. Doesn't mean that they don't exist of course :)

>
> RIOT OS already supports the HiFive E310 RISC-V MCU, but that is a
> very different piece of hardware with RISC-V Privileged Architecture
> support. Still I've been able to reuse some code chunks.
I happen to be working on refactoring the fe310 code to split out the
common RISC-V code bits. Mainly to support the gd32vf103 devices from
Gigadevice, but any RISC-V MCU should benefit from this. It should at
least simplify your porting work in the future.
>
> So far It's only an experiment (and I'm a newbie at this!), but all
> the important features already work, including shell over UART. It is
> really fascinating to be able to use a tiny FPGA board this way.
(Personally) I think this makes for a great addition to RIOT. Support
for a softcore really opens a lot of options for designers.
>
> If you are interested, you can find the (alpha, experimental!) code at:
>
> https://github.com/tstyblo/RIOT-icoboard
>
> It would make no sense trying to merge it into the mainline now, as
> the code needs a lot of testing, comments and improvements. But I'd
> like to use this opportunity to invite anyone interested in FPGA
> devices or in the RISC-V platform to check it out.

Looks awesome, thanks for sharing. Is there also a repository with the
verilog for the FPGA configuration? Any estimation how many LUT's and
other resources it requires from the FPGA?

Best regards,

Koen Zandberg


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