[riot-notifications] [RIOT-OS/RIOT] cpu/arm7_common: Make irq_*() compiler barriers (#11440)
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Wed Apr 24 17:22:47 CEST 2019
### Contribution description
Previously the compiler was allowed to reorder access to the interrupt control registers in regard to memory access not marked as `volatile` (at least some people - most notably some compiler developers - read the C standard this way). In practise this did not happen as irq_disable(), irq_restore(), irq_enable() are part of a separate compilation unit: Calls to external functions unknown to the compiler are treated as if they were memory barriers. But if link time optimization (LTO) is enabled, this no longer would work: The compiler could inline the code accessing the interrupt control registers and reorder the memory accesses wrapped in irq_disable() and irq_restore() outside of their protection.
This commit adds the "memory" clobber to the inline assembly accessing the interrupt control registers. This makes those accesses explicit compiler memory barriers. The machine code generated without LTO enabled should not differ in any way by this commit. But the use of irq_*() should now be safe with LTO.
### Testing procedure
Compile some application for an ARMv7 (no CortexM) board, e.g. the MSB-A2. Without LTO no differences before and after this PR should be present, with this PR they could be present.
E.g. here is the output of [elf_diff](https://github.com/CapeLeidokos/elf_diff/) generated for the binaries in `examples/default` generated by:
- `make BOARD=msba2` https://mari-bu.de/without_lto.html
- `make BOARD=msba2 LTO=yes` https://mari-bu.de/with_lto.html
### Issues/PRs references
Related to https://github.com/RIOT-OS/RIOT/pull/11438, as this implements the barrier claimed to be present in the doc there
You can view, comment on, or merge this pull request online at:
-- Commit Summary --
* cpu/arm7_common: Make irq_*() compiler barriers
-- File Changes --
M cpu/arm7_common/VIC.c (6)
-- Patch Links --
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