[riot-notifications] [RIOT-OS/RIOT] drivers: net: add ethocan (Ethernet-over-CAN) driver (#10710)

Juergen Fitschen notifications at github.com
Mon Jan 7 23:27:56 CET 2019


### Further testing: Sense pin delay for frame reception

I attached a logic analyzer to some GPIOs of the *Bluepill* and added some code lines in order to output the current state of the state machine:
 * `P_IN_FSM`: Is set high, once the FSM is entered. This happens every time, once some ISR related to *ethocan* is executed. After the FSM has been processed, the pin is cleared.
 * `P_FSM_0..P_FSM_2`: Binary representation of the current state. These pins are valid once `P_IN_FSM` has a falling edge. States:
   * **BLOCKED**: 1
   * **IDLE**: 2
   * **RECV**: 3
   * **SEND**: 4

The result (sampled with 200MHz) shows that the interrupt delay is about 3us:
![int_delay](https://user-images.githubusercontent.com/6105784/50796810-1d456f80-12d3-11e9-8b7a-317ff5212859.png)

This patch:
```diff
diff --git a/drivers/ethocan/ethocan.c b/drivers/ethocan/ethocan.c
index d6b5a39ce..264684e7a 100644
--- a/drivers/ethocan/ethocan.c
+++ b/drivers/ethocan/ethocan.c
@@ -30,6 +30,11 @@
 #define ENABLE_DEBUG (0)
 #include "debug.h"

+#define P_IN_FSM GPIO_PIN(PORT_A,  8)
+#define P_FSM_0  GPIO_PIN(PORT_A,  9)
+#define P_FSM_1  GPIO_PIN(PORT_A, 10)
+#define P_FSM_2  GPIO_PIN(PORT_A, 11)
+
 static uint16_t crc16_update(uint16_t crc, uint8_t octet);
 static uint8_t state_blocked(ethocan_t *ctx, uint8_t old_state);
 static uint8_t state_recv(ethocan_t *ctx, uint8_t old_state);
@@ -162,6 +167,7 @@ static uint8_t state(ethocan_t *ctx, uint8_t src)
     /* Make sure no other thread or ISR interrupts state transitions */
     int irq_state = irq_disable();

+    gpio_set(P_IN_FSM);
     uint8_t old_state = ctx->state;
     uint8_t new_state = ETHOCAN_STATE_UNDEF;

@@ -242,6 +248,10 @@ static uint8_t state(ethocan_t *ctx, uint8_t src)
     mutex_unlock(&ctx->state_mtx);

 exit:
+    gpio_write(P_FSM_0, new_state & 0b001);
+    gpio_write(P_FSM_1, new_state & 0b010);
+    gpio_write(P_FSM_2, new_state & 0b100);
+    gpio_clear(P_IN_FSM);
     irq_restore(irq_state);
     return ctx->state;
 }
@@ -533,6 +543,11 @@ void ethocan_setup(ethocan_t *ctx, const ethocan_params_t *params)
     gpio_init_int(ctx->sense_pin, GPIO_IN, GPIO_FALLING, _isr_gpio, (void *) ctx);
     gpio_irq_disable(ctx->sense_pin);

+    gpio_init(P_IN_FSM, GPIO_OUT);
+    gpio_init(P_FSM_0, GPIO_OUT);
+    gpio_init(P_FSM_1, GPIO_OUT);
+    gpio_init(P_FSM_2, GPIO_OUT);
+
     luid_get(ctx->mac_addr, ETHERNET_ADDR_LEN);
     ctx->mac_addr[0] &= (0x2);
     ctx->mac_addr[0] &= ~(0x1);
```

(Sorry for being spammy ...)

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