[riot-notifications] [RIOT-OS/RIOT] cpu/kinetis/rtt: clear TPR when writing TSR (#10764)

Thomas Stilwell notifications at github.com
Mon Jan 14 08:31:33 CET 2019

The RIOT community cares a lot about code quality.
Therefore, before describing what your contribution is about, we would like
you to make sure that your modifications are compliant with the RIOT
coding conventions, see https://github.com/RIOT-OS/RIOT/wiki/Coding-conventions.

### Contribution description
Currently the `periph_rtt` implementation for `kinetis` ignores the subsecond RTC register (`RTC->TPR`). As a result, when `rtc_set_time()` is called, the RTC is left with a known second count but an unknown subsecond count.

This means that setting the RTC incurs an error of +/-1 second.

This PR clears the subsecond register `RTC->TPR` while setting the second register `RTC->TSR` to the requested value so that the RTC is left unambiguously set to the requested time.
Put here the description of your contribution:
- describe which part(s) of RIOT is (are) involved
- if it's a bug fix, describe the bug that it solves and how it is solved
- you can also give more information to reviewers about how to test your changes

### Testing procedure
Using #10763, run `tests/periph_rtc` with and without this PR on a `kw41z` or other `kinetis` platform.

The RTC alarm error output from the test should be always minimal (<100us) with this PR. Without it, the error will vary +/-1 second and will depend on how and when the last reset occurred. In particular, a power-on reset will synchronize the RTC clock domain and cause good error offsets even without this PR until the next non-POR reset.

Details steps to test your contribution:
- which test/example to compile for which board and is there a 'test' command
- how to know that it was not working/available in master
- the expected success test output

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-- Commit Summary --

  * cpu/kinetis/rtt: clear subseconds when writing seconds

-- File Changes --

    M cpu/kinetis/periph/rtt.c (2)

-- Patch Links --


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