[riot-notifications] [RIOT-OS/RIOT] cpu/stm32/i2c: Fix error flag clearing in sr1 (#11728)

MrKevinWeiss notifications at github.com
Thu Jun 20 15:55:55 CEST 2019

### Contribution description
This commit fixes the clearing of a error condition after read.
This causes the incorrect errorcodes if the register is read
then an error occurs, then it is cleared.
By clearing only after the error is processed the bug is fixed.
This can be tested by reading a i2c slave that is not there.

Discovered by the HiL i2c tests.

### Testing procedure
- run `tests/periph_i2c` on any F1, F2, L1, and F4 without anything connected
- acquire the bus
- spam read register requests to get the `ENXIO` error

On master there will be occasional `ETIMEDOUT` errors due to the SR1 being read, then after being read but before getting cleared the AF error bit is set, then it gets cleared without ever being read into the buffer.  The definition of a volatile register :)

### Issues/PRs references

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-- Commit Summary --

  * cpu/stm32/i2c: Fix error flag clearing in sr1

-- File Changes --

    M cpu/stm32_common/periph/i2c_2.c (6)

-- Patch Links --


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