[riot-notifications] [RIOT-OS/RIOT] sam0: Implement watchdog driver (#11520)

Kees Bakker notifications at github.com
Thu May 16 21:36:48 CEST 2019


Here is my suggestion for clock setup, using GCLK4. The code and comments are from @GabrielNotman in Arduino library Sodaq_wdt.
```
static void _wdt_clock_setup(void)
{
    /* Setup clock provider WDT_GCLK with a 32 source divider
     * GCLK_GENDIV_ID(X), specifies which GCLK we are configuring
     * GCLK_GENDIV_DIV(Y), specifies the clock prescalar / divider
     * If GENCTRL.DIVSEL is set (see further below) the divider 
     * is 2^(Y+1). If GENCTRL.DIVSEL is 0, the divider is simply Y
     * This register has to be written in a single operation
     */
    GCLK->GENDIV.reg = GCLK_GENDIV_ID(WDT_GCLK) | 
                       GCLK_GENDIV_DIV(4);

    /* Configure the GCLK module
     * GCLK_GENCTRL_GENEN, enable the specific GCLK module
     * GCLK_GENCTRL_SRC_OSCULP32K, set the source to the OSCULP32K
     * GCLK_GENCTRL_ID(X), specifies which GCLK we are configuring
     * GCLK_GENCTRL_DIVSEL, specify which prescalar mode we are using
     * Output from this module is 1khz (32khz / 32)
     * This register has to be written in a single operation.
     */
    GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | 
                        GCLK_GENCTRL_SRC_OSCULP32K | 
                        GCLK_GENCTRL_ID(WDT_GCLK) | 
                        GCLK_GENCTRL_DIVSEL;
    while (GCLK->STATUS.bit.SYNCBUSY) {}
    
    /* Configure the WDT clock
     * GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_WDT), specify the WDT clock
     * GCLK_CLKCTRL_GEN(WDT_GCLK), specify the source from the WDT_GCLK GCLK
     * This register has to be written in a single operation
     */
    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_WDT) |
                        GCLK_CLKCTRL_GEN(WDT_GCLK) | 
                        GCLK_CLKCTRL_CLKEN;
    while (GCLK->STATUS.bit.SYNCBUSY) {}
}
```

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