[riot-notifications] [RIOT-OS/RIOT] cpu/sam0: add support for SAMD5x/SAME5x (#11305)

Dylan Laduranty notifications at github.com
Thu May 23 14:24:18 CEST 2019


dylad commented on this pull request.

Another small round.
We should be good now.

> +    while (!(GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg & GCLK_PCHCTRL_CHEN)) {}
+
+    GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL032K].reg = GCLK_PCHCTRL_GEN(1)
+                             | GCLK_PCHCTRL_CHEN;
+    while (!(GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL032K].reg & GCLK_PCHCTRL_CHEN)) {}
+}
+
+static void dpll0_init(uint32_t f_cpu)
+{
+    const uint32_t LDR = ((f_cpu * 16) / 32768);
+
+    OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(LDR % 16)
+                       | OSCCTRL_DPLLRATIO_LDR((LDR / 16) - 1);
+
+    OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_XOSC32
+                       | OSCCTRL_DPLLCTRLB_DIV(1)

Not needed.

> +
+static void dpll0_init(uint32_t f_cpu)
+{
+    const uint32_t LDR = ((f_cpu * 16) / 32768);
+
+    OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(LDR % 16)
+                       | OSCCTRL_DPLLRATIO_LDR((LDR / 16) - 1);
+
+    OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_XOSC32
+                       | OSCCTRL_DPLLCTRLB_DIV(1)
+                       | OSCCTRL_DPLLCTRLB_WUF
+                       | OSCCTRL_DPLLCTRLB_LBYPASS;
+
+    OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
+
+    while (!OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY ||

isn't better with && instead of || ?

> @@ -0,0 +1,9 @@
+/**
+ * @defgroup        cpu_samd5x Atmel SAMD5x/SAME5x

Microchip
here and everywhere at the same time

> +
+/**
+ * @brief   Override SPI hardware chip select macro
+ *
+ * As of now, we do not support HW CS, so we always set it to a fixed value
+ */
+#define SPI_HWCS(x)     (UINT_MAX - 1)
+
+/**
+ * @brief   PWM channel configuration data structure
+ */
+typedef struct {
+    gpio_t pin;                 /**< GPIO pin */
+    gpio_mux_t mux;             /**< pin function multiplex value */
+    uint8_t chan;               /**< TCC channel to use */
+} pwm_conf_chan_t;

you can remove this unless you plan to add the pwn driver with this PR :)

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