[riot-notifications] [RIOT-OS/RIOT] cpu/arm7_common: Make irq_*() compiler barriers (#11440)

Gunar Schorcht notifications at github.com
Fri May 24 00:20:12 CEST 2019

@maribu I am not sure whether any problem could occur with the following code in `irq_disable`/`irq_enable`:
    uint32_t _saved_intlevel;
    __asm__ volatile ("rsil %0, 0" : "=a" (_saved_intlevel));
    _saved_intlevel &= 0xf;
    return _saved_intlevel;
Local variables are hold in registers and the compiler produces the following instructions for the code above:
    rsil   a2, 0
    extui  a2, a2, 0, 4
The return value is stored in `a2`.

Xtensa Instruction Set Architecture (ISA) Reference Manual says:
_`RSIL` first reads the `PS` Special Register, writes this value to address register at, and then sets `PS.INTLEVEL` to a constant in the range 0..15 encoded in the instruction word. ... The instruction following the `RSIL` is guaranteed to be executed at the new interrupt level specified in `PS.INTLEVEL`, therefore it is not necessary to insert one of the `SYNC` instructions to force the interrupt level change to take effect._

`rsil` is a single instruction and the old interrupt level is stored in register` a2` in any case before the new interrupt level is set. Even if a context switch would happen between `rsil` and the following `extui` to extract the lowest four bits, it shouldn't be a problem.

The code produced for `irq_restore`
    __asm__ volatile ("wsr %0, ps; rsync" :: "a" (state));
is of course
   wsr.ps  a2
where `a2` contains the new interrupt level as parameter.

Xtensa Instruction Set Architecture (ISA) Reference Manual says:
_`RSYNC` waits for all previously fetched `WSR.*` instructions to be performed before interpreting the register fields of the next instruction._

You are receiving this because you are subscribed to this thread.
Reply to this email directly or view it on GitHub:
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.riot-os.org/pipermail/notifications/attachments/20190523/fd5ecc20/attachment-0001.html>

More information about the notifications mailing list