[riot-notifications] [RIOT-OS/RIOT] cpu/sam0: add support for SAMD5x/SAME5x (#11305)

benpicco notifications at github.com
Mon May 27 21:09:38 CEST 2019

This keeps puzzling me.
If I source the GCLK5 from e.g. FDPLL1 configured to tun at at 16MHz with prescaler 16, all test run fine and the offset in `xtimer_usleep` is ~33µs, but this is at the expense of a higher power consumption of around 2 mA.

When I use the 48 MHz DFLL I get

- Offset: ~4300µs with `GCLK_GENCTRL_DIV(12)` & `TC_CTRLA_PRESCALER_DIV4` 
- Offset: ~4300µs with `GCLK_GENCTRL_DIV(6)` & `TC_CTRLA_PRESCALER_DIV8` 
- Offset: ~5µs with with `GCLK_GENCTRL_DIV(3)` & `TC_CTRLA_PRESCALER_DIV16` but with bursts of 5000µs

With 120 MHz DPLL0 :
- Offset: ~5000µs with `GCLK_GENCTRL_DIV(120)` & `TC_CTRLA_PRESCALER_DIV1` 
- Offset: ~5000µs with `GCLK_GENCTRL_DIV(15)` & `TC_CTRLA_PRESCALER_DIV8` 
- Offset: ~5µs with `GCLK_GENCTRL_DIV(4)` & `TC_CTRLA_PRESCALER_DIV16` but with burst of 4600µs - and the clock is wrong.
- Offset: 6µs with `GCLK_GENCTRL_DIV(2)` & `TC_CTRLA_PRESCALER_DIV64` - but now the clock is wrong

Only when I overclock the CPU to 128 MHz I get both a stable and *correct* clock.

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