[riot-notifications] [RIOT-OS/RIOT] cpu/fe310: fixes for SW interrupt latency issues (#12196)

Kaspar Schleiser notifications at github.com
Tue Sep 10 21:43:25 CEST 2019

kaspar030 commented on this pull request.

 void thread_yield_higher(void)
     /* Use SW intr to schedule context switch */
+    /* Latency of SW intr can be 4-7 cycles; delay 8 cycles */

could we wait for a volatile variable?

static volatile int _barrier;
void thread_yield_higher(void) {
  int barrier_before = _barrier;
  while (_barrier == barrier_before); {}

... and in the isr do ```_barrier++```. This might need compiler barriers.
Not sure this would actually be shorter than a couple of nops.

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