[riot-notifications] [RIOT-OS/RIOT] cpu/fe310: fixes for SW interrupt latency issues (#12196)
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Tue Sep 10 22:04:06 CEST 2019
benpicco commented on this pull request.
/* Use SW intr to schedule context switch */
CLINT_REG(CLINT_MSIP) = 1;
+ /* Latency of SW intr can be 4-7 cycles; delay 8 cycles */
With [Compiler Explorer](https://godbolt.org/) when building with `-Os` this generates
#### with Clang for rv32g
thread_yield_higher(): # @thread_yield_higher()
lui a0, %hi(_barrier)
lw a1, %lo(_barrier)(a0)
lui a2, 8192
addi a3, zero, 1
sw a3, 0(a2)
.LBB0_1: # =>This Inner Loop Header: Depth=1
lw a2, %lo(_barrier)(a0)
beq a2, a1, .LBB0_1
.word 0 # 0x0
#### RISC-V gcc 8.2
Looks like at least 8 instructions either way, so we are not saving anything compared to the nop-slide.
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