[riot-notifications] [RIOT-OS/RIOT] cpu/fe310: fixes for SW interrupt latency issues (#12196)
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Tue Sep 10 23:12:31 CEST 2019
kenrabold commented on this pull request.
/* Use SW intr to schedule context switch */
CLINT_REG(CLINT_MSIP) = 1;
+ /* Latency of SW intr can be 4-7 cycles; delay 8 cycles */
Actually, yes WFI is on RISC-V and it will catch the SW interrupt. I tried it out and the implementation looks much cleaner.
Also, there were problems with debugging and WFI on the HiFive1 which are now fixed on HiFive1B with the Segger JTAG interface. So I'm I'd like to enable that in `pm_set_lowest `(it was previously commented out).
I'll adjust the PR
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