[riot-notifications] [RIOT-OS/RIOT] TI CC3200 SimpleLink RIOT support (#11866)

benpicco notifications at github.com
Sun May 24 02:08:28 CEST 2020


@benpicco commented on this pull request.



> +}
+
+void spi_init(spi_t bus)
+{
+    /* assert(bus >= SPI_NUMOF); */
+    mutex_init(&locks[bus]);
+
+    /* CC3100 module does not require pin config */
+    if (bus != CC3100_SPI) {
+        /* trigger pin initialization */
+        spi_init_pins(bus);
+    }
+
+    /* enable clock */
+    switch (bus) {
+    case EXTERNAL_SPI:

`bus * 0x1C`? What are you trying to do?

I noticed you have `LSPI_BASE` and `GSPI_BASE` in `base_addr`. Will `LSPI_BASE` always be controlled through `MCSPI_A1`?

Or does `gpio_port == 0` map to `MCSPI_A1` and `gpio_port == 1` to `MCSPI_A2`?

And what's with `PRCM_SLP_MODE_CLK`?
 

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