[riot-notifications] [RIOT-OS/RIOT] boards/stm32f1f3: model clock configuration in Kconfig (#15001)

Alexandre Abadie notifications at github.com
Fri Nov 27 08:56:22 CET 2020


@aabadie commented on this pull request.



>  config CLOCK_PLL_PREDIV
-    int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6
-    default 2 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6
+    int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6 && !CPU_LINE_STM32F303X8
+    # iotlab based boards provide a 16MHz HSE so they need a predivider of 2
+    # to remain with a 72MHz sysclk by default.
+    default 2 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 || CPU_LINE_STM32F303X8 || (CPU_FAM_F1 && (BOARD_IOTLAB_M3 || BOARD_IOTLAB_A8_M3 || BOARD_FOX))

What kind of feature could you imagine ?
For f0/f3, we could define a symbol `CLOCK_PLL_NO_PREDIV` that is false by default and select it in the CPU families that have this limitation. And here that would just be `default 2 if CLOCK_PLL_NO_PREDIV`.
For the iotlab boards case, it's more complicated since it depends on the HSE clock frequency. I have no idea how to solve this cleanly. With f2/f4/f7, this will become even more difficult to manage since there are more HSE values (12MHz, 16MHz, 25MHz, etc)

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