[riot-notifications] [RIOT-OS/RIOT] cpu/avr8_common: Improve isr state for nested interrupts (#16211)

Marian Buschsieweke notifications at github.com
Tue Apr 6 17:07:17 CEST 2021


> Maybe I not explained properly. The main objective is have ATxmega working in a multi thread with nested ISR enabled.

OK, I see.

I had another look at the status register of the ATXmega. If I read it correctly, the status register should be enough to deduce the current level of nesting. E.g. the layout is:

> ```
>      7          6          5          4          3          2          1          0
> +----------+-------------------------------------------+----------+----------+----------+
> |  NMIEX   |     reserved                              | HILVLEX  | MEDLVLEX | LOLVLEX  |
> +----------+-------------------------------------------+----------+----------+----------+
> ```
> 
> - Bit 7 – NMIEX: Non-Maskable Interrupt ExecutingThis flag is set if a non-maskable interrupt is executing. The flag will be cleared when returning (RETI) from the interrupt handler.
> - Bit 6:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
> - Bit 2 – HILVLEX: High-level Interrupt ExecutingThis flag is set when a high-level interrupt is executing or when the interrupt handler has been interrupted by an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
> - Bit 1 – MEDLVLEX: Medium-level Interrupt ExecutingThis flag is set when a medium-level interrupt is executing or when the interrupt handler has been interrupted by an interrupt from higher level or an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
> - Bit 0 – LOLVLEX: Low-level Interrupt ExecutingThis flag is set when a low-level interrupt is executing or when the interrupt handler has been interrupted by an interrupt from higher level or an NMI. The flag will be cleared when returning (RETI) from the interrupt

I understand this as e.g. `0b00000101` would mean that currently a high priority ISR is running that interrupted a previously running low priority ISR. And e.g. `0b00000100` would be a high prio ISR that interrupted thread context.

So, there is no need to manually monitor nesting depth. And hence, nested IRQs should work fine without custom ISR epilog and prologs.

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