[riot-notifications] [RIOT-OS/RIOT] riscv_common: Refactor common fe310 code to riscv_common (#15718)
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Tue Jan 26 12:01:01 CET 2021
> I'm not sure that declaring the coretimer/plic as peripherals is the way to go. You could simply add them to the riscv_common module. But maybe I'm missing something here ?
Me neither. The issue is that the PLIC is one of the possible implementations for interrupt controllers on the RISC-V. There is also the [CLIC](https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc). A CPU could use the CLINT timer for periph_timer, but it could also use a different (more advanced) timer peripheral
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