[riot-notifications] [RIOT-OS/RIOT] tests/periph_spi: add support for printing and testing SPI clock rate… (#16727)

Hugues Larrive notifications at github.com
Wed Sep 1 05:33:31 CEST 2021


# Some tests:
## nucleo-f746zg
```
init
2021-09-01 04:35:48,096 # init
2021-09-01 04:35:48,101 # usage: init <dev> <mode> <clk> [cs port] [cs pin]
2021-09-01 04:35:48,101 # 	dev:
2021-09-01 04:35:48,103 # 		0: SPI_DEV(0)
2021-09-01 04:35:48,104 # 		1: SPI_DEV(1)
2021-09-01 04:35:48,105 # 	mode:
2021-09-01 04:35:48,109 # 		0: POL:0, PHASE:0 - on first rising edge
2021-09-01 04:35:48,112 # 		1: POL:0, PHASE:1 - on second rising edge
2021-09-01 04:35:48,116 # 		2: POL:1, PHASE:0 - on first falling edge
2021-09-01 04:35:48,120 # 		3: POL:1, PHASE:1 - on second falling edge
2021-09-01 04:35:48,120 # 	clk:
2021-09-01 04:35:48,123 # 		0: SPI_CLK_100KHZ (421875 Hz)
2021-09-01 04:35:48,126 # 		1: SPI_CLK_400KHZ (421875 Hz)
2021-09-01 04:35:48,128 # 		2: SPI_CLK_1MHZ (843750 Hz)
2021-09-01 04:35:48,131 # 		3: SPI_CLK_5MHZ (3375000 Hz)
2021-09-01 04:35:48,133 # 		4: SPI_CLK_10MHZ (6750000 Hz)
2021-09-01 04:35:48,136 # 		n: arbitrary value in Hz
2021-09-01 04:35:48,137 # 	cs port:
2021-09-01 04:35:48,142 # 		Port of the CS pin, set to -1 for hardware chip select
2021-09-01 04:35:48,143 # 	cs pin:
2021-09-01 04:35:48,149 # 		Pin used for chip select. If hardware chip select is enabled,
2021-09-01 04:35:48,153 # 		this value specifies the internal HWCS line
init 0 0 1700000 0 0
2021-09-01 04:36:11,845 # init 0 0 1700000 0 0
2021-09-01 04:36:11,852 # SPI_DEV(0) initialized: mode: 0, clk: 1700000(1687500 Hz),cs_port: 0, cs_pin: 0
> init 0 0 14000000 0 0
2021-09-01 04:37:16,051 # init 0 0 14000000 0 0
2021-09-01 04:37:16,058 # SPI_DEV(0) initialized: mode: 0, clk: 14000000(13500000 Hz),cs_port: 0, cs_pin: 0
> init 0 0 27000000 0 0
2021-09-01 04:37:41,326 # init 0 0 27000000 0 0
2021-09-01 04:37:41,333 # SPI_DEV(0) initialized: mode: 0, clk: 27000000(27000000 Hz),cs_port: 0, cs_pin: 0
> init 0 0 54000000 0 0
2021-09-01 04:37:51,521 # init 0 0 54000000 0 0
2021-09-01 04:37:51,529 # SPI_DEV(0) initialized: mode: 0, clk: 54000000(54000000 Hz),cs_port: 0, cs_pin: 0
> init 0 0 108000000 0 0
2021-09-01 04:38:09,621 # init 0 0 108000000 0 0
2021-09-01 04:38:09,628 # SPI_DEV(0) initialized: mode: 0, clk: 108000000(54000000 Hz),cs_port: 0, cs_pin: 0
```
All clock rates are accessible now.
## esp8266-esp-12x
```
init
2021-09-01 04:41:04,630 # init
2021-09-01 04:41:04,654 # usage: init <dev> <mode> <clk> [cs port] [cs pin]
2021-09-01 04:41:04,654 # 	dev:
2021-09-01 04:41:04,655 # 		0: SPI_DEV(0)
2021-09-01 04:41:04,655 # 	mode:
2021-09-01 04:41:04,656 # 		0: POL:0, PHASE:0 - on first rising edge
2021-09-01 04:41:04,657 # 		1: POL:0, PHASE:1 - on second rising edge
2021-09-01 04:41:04,658 # 		2: POL:1, PHASE:0 - on first falling edge
2021-09-01 04:41:04,659 # 		3: POL:1, PHASE:1 - on second falling edge
2021-09-01 04:41:04,674 # 	clk:
2021-09-01 04:41:04,675 # 		0: SPI_CLK_100KHZ (100000 Hz)
2021-09-01 04:41:04,676 # 		1: SPI_CLK_400KHZ (400000 Hz)
2021-09-01 04:41:04,677 # 		2: SPI_CLK_1MHZ (1000000 Hz)
2021-09-01 04:41:04,678 # 		3: SPI_CLK_5MHZ (5000000 Hz)
2021-09-01 04:41:04,679 # 		4: SPI_CLK_10MHZ (10000000 Hz)
2021-09-01 04:41:04,679 # 	cs port:
2021-09-01 04:41:04,681 # 		Port of the CS pin, set to -1 for hardware chip select
2021-09-01 04:41:04,681 # 	cs pin:
2021-09-01 04:41:04,683 # 		Pin used for chip select. If hardware chip select is enabled,
2021-09-01 04:41:04,685 # 		this value specifies the internal HWCS line
> init 0 0 5 0 0
2021-09-01 04:42:07,981 # init 0 0 5 0 0
2021-09-01 04:42:07,984 # error: invalid bus speed specified
```
The driver do not supports arbitrary bus speed.
## atmega1284p
```
2021-09-01 04:50:41,813 # init
2021-09-01 04:50:41,865 # usage: init <dev> <mode> <clk> [cs port] [cs pin]
2021-09-01 04:50:41,871 # 	dev:
2021-09-01 04:50:41,888 # 		0: SPI_DEV(0)
2021-09-01 04:50:41,895 # 	mode:
2021-09-01 04:50:41,940 # 		0: POL:0, PHASE:0 - on first rising edge
2021-09-01 04:50:41,986 # 		1: POL:0, PHASE:1 - on second rising edge
2021-09-01 04:50:42,031 # 		2: POL:1, PHASE:0 - on first falling edge
2021-09-01 04:50:42,078 # 		3: POL:1, PHASE:1 - on second falling edge
2021-09-01 04:50:42,084 # 	clk:
2021-09-01 04:50:42,117 # 		0: SPI_CLK_100KHZ (62500 Hz)
2021-09-01 04:50:42,150 # 		1: SPI_CLK_400KHZ (250000 Hz)
2021-09-01 04:50:42,181 # 		2: SPI_CLK_1MHZ (500000 Hz)
2021-09-01 04:50:42,213 # 		3: SPI_CLK_5MHZ (2000000 Hz)
2021-09-01 04:50:42,247 # 		4: SPI_CLK_10MHZ (4000000 Hz)
2021-09-01 04:50:42,257 # 	cs port:
2021-09-01 04:50:42,316 # 		Port of the CS pin, set to -1 for hardware chip select
2021-09-01 04:50:42,326 # 	cs pin:
2021-09-01 04:50:42,392 # 		Pin used for chip select. If hardware chip select is enabled,
2021-09-01 04:50:42,440 # 		this value specifies the internal HWCS line
```
The resulting speeds displayed are half of the targeted speeds because the `spi_clk_t enum` from `cpu/atmega_common/periph_cpu.h` has been written assuming a master clock speed of 16 MHz, but this card operates at only 8 MHz. So this which is displayed is what you really get on the SCK PIN.

## Other architectures
I have not the hardware to make tests on other architectures.

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