<p><b>@Former</b> commented on this pull request.</p>

<hr>

<p>In <a href="https://github.com/RIOT-OS/RIOT/pull/11258#discussion_r269472890">cpu/stm32_common/periph/rtc.c</a>:</p>
<pre style='color:#555'>> +        // Resets the entire Backup domain
+        RCC->BDCR |= RCC_BDCR_BDRST;
+        // Reset not activated
+        RCC->BDCR &= ~RCC_BDCR_BDRST;
+
+        //RTC clock enabled
+        //LSE oscillator clock used as RTC clock10: LSI oscillator clock used as RTC clock
+        RCC->BDCR |= RCC_BDCR_RTCEN | RCC_BDCR_RTCSEL_LSE;
+
+        // Second interrupt is enabled.
+        RTC->CRH |= RTC_CRH_SECIE;
+
+        // Enter configuration mode.
+        RTC->CRL |= RTC_CRL_CNF;
+
+        //If the input clock frequency (fRTCCLK) is 32.768 kHz, write 7FFFh in this register to get a signal period of 1 second.
</pre>
<p>Yes, 0x7fff will be correct</p>

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