<p><b>@dylad</b> commented on this pull request.</p>

<hr>

<p>In <a href="https://github.com/RIOT-OS/RIOT/pull/11305#discussion_r286948661">cpu/samd5x/cpu.c</a>:</p>
<pre style='color:#555'>> +    while (!(GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg & GCLK_PCHCTRL_CHEN)) {}
+
+    GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL032K].reg = GCLK_PCHCTRL_GEN(1)
+                             | GCLK_PCHCTRL_CHEN;
+    while (!(GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL032K].reg & GCLK_PCHCTRL_CHEN)) {}
+}
+
+static void dpll0_init(uint32_t f_cpu)
+{
+    const uint32_t LDR = ((f_cpu * 16) / 32768);
+
+    OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(LDR % 16)
+                       | OSCCTRL_DPLLRATIO_LDR((LDR / 16) - 1);
+
+    OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_XOSC32
+                       | OSCCTRL_DPLLCTRLB_DIV(1)
</pre>
<p>It doesn't hurt but it is completely useless because you are setting the divider for XOSC but you are using XOSC32 ;)<br>
check Figure 28-2. DPLL Block Diagram of the datasheet</p>

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