<p><b>@dylad</b> commented on this pull request.</p>

<hr>

<p>In <a href="https://github.com/RIOT-OS/RIOT/pull/11655#discussion_r295346042">cpu/samd5x/cpu.c</a>:</p>
<pre style='color:#555'>>  
     OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(LDR & 0x1F)
-                       | OSCCTRL_DPLLRATIO_LDR((LDR >> 5) - 1);
+                                   | OSCCTRL_DPLLRATIO_LDR((LDR >> 5) - 1);
</pre>
<p>Could you add while (OSCCTRL->Dpll[0].DPLLSYNCBUSY.reg) {} after this call and another one after the enable because these registers are write synchronized.<br>
I am happy with the changes, you can squash directly.</p>

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