<p>I dug into this issue deeper and found that the reason for the <code>thread_race</code> and <code>thread_msg_block_race</code> failures was that when <code>thread_yield_higher</code> invokes a SW interrupt, the FE310 can take up to 4-7 cycles to respond. As a result, assembly instructions after the call to <code>thread_yield_higher </code>in the current active thread will be executed resulting in possible old data within registers. The 2 test programs I referenced produce that effect and is similar to <a class="issue-link js-issue-link" data-error-text="Failed to load issue title" data-id="312223814" data-permission-text="Issue title is private" data-url="https://github.com/RIOT-OS/RIOT/issues/8897" data-hovercard-type="pull_request" data-hovercard-url="/RIOT-OS/RIOT/pull/8897/hovercard" href="https://github.com/RIOT-OS/RIOT/pull/8897">#8897</a></p>
<p>Your simulator would not have had this issue as I'm sure you are not introducing a latency in the simulation of interrupts.</p>
<p>To fix this, I added 8 nops after invoking the SW interrupt. I also addressed the thread_yield call and the issue referenced in <a class="issue-link js-issue-link" data-error-text="Failed to load issue title" data-id="486484123" data-permission-text="Issue title is private" data-url="https://github.com/RIOT-OS/RIOT/issues/12110" data-hovercard-type="issue" data-hovercard-url="/RIOT-OS/RIOT/issues/12110/hovercard" href="https://github.com/RIOT-OS/RIOT/issues/12110">#12110</a></p>
<p>My changes are here: <a href="url">https://github.com/kenrabold/RIOT/blob/pr_thread_yield_higher/cpu/fe310/cpu.c</a></p>
<p>You can update your PR with these changes, or I can request the PR to pull in these fixes.</p>
<p>Thanks for finding this and calling it out. Good bug</p>

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