<p></p>
<p><b>@bergzand</b> commented on this pull request.</p>

<hr>

<p>In <a href="https://github.com/RIOT-OS/RIOT/pull/15420#discussion_r565959591">cpu/stm32/periph/flashpage.c</a>:</p>
<pre style='color:#555'>> +#ifdef FLASH_ACR_DCEN
+    if (FLASH->ACR & FLASH_ACR_DCEN) {
+        FLASH->ACR &= ~FLASH_ACR_DCEN;
+    }
+#endif
+#ifdef FLASH_ACR_ICEN
+    if (FLASH->ACR & FLASH_ACR_ICEN) {
+        FLASH->ACR &= ~FLASH_ACR_ICEN;
+    }
+#endif
</pre>
<p>Data and instruction caches, clarified with a comment</p>

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