<p></p>
<p><b>@fabian18</b> commented on this pull request.</p>

<hr>

<p>In <a href="https://github.com/RIOT-OS/RIOT/pull/16609#discussion_r663963371">cpu/rp2040/cpu.c</a>:</p>
<pre style='color:#555'>> +            RESETS_RESET_spi1_Msk       |
+            RESETS_RESET_spi0_Msk       |
+            RESETS_RESET_rtc_Msk        |
+            RESETS_RESET_adc_Msk);
+    periph_reset_done(rst);
+
+    /* power the reference clock from its default source: the ROSC */
+    clock_ref_configure_source(MHZ(12), MHZ(12), CLOCKS_CLK_REF_CTRL_SRC_rosc_clksrc_ph);
+    /* power the system clock from its default source: the reference clock */
+    clock_sys_configure_source(MHZ(12), MHZ(12), CLOCKS_CLK_SYS_CTRL_SRC_clk_ref);
+    /* start XOSC running at 12 MHz */
+    xosc_start(MHZ(12));
+    /* reset system PLL */
+    pll_reset_sys();
+    /* make the system PLL output a 125 MHz frequency from the 12 MHz XOSC */
+    pll_start_sys(MHZ(12), 1, 125, 6, 2);
</pre>
<p>PLL configuration values:<br>
<code>12 MHz</code> input frequency from the <code>XTAL</code>,<br>
divided by  <code>1</code>,<br>
scaled with <code>125</code> by the <code>PLL</code>,<br>
post-divided by <code>(6 * 2)</code> ,<br>
makes <code>125</code> MHz.</p>

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